Digital Design Challenge

Digital Design Challenge - techFEST'26 For Non-SLIET Participants Only techFEST'26 is North India's premier technical festival, organised by Sant Longowal Institute of Engineering and Technology (SLIET), Longowal, Punjab. This is a paid opportunity with the early-bird packages mentioned below.

Official Website: https://www.techfest26.com

Note: Registration is mandatory for participation. Fee once paid is non-refundable.

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Accommodation and Meals: Registration for the techFEST’26 package is compulsory for accommodation and other perks, while participation in individual events is free*.

About the Event: Digital Design Challenge is an individual competition designed to test participants' knowledge and practical skills in digital logic and Hardware Description Languages (HDLs). The challenge focuses on designing combinational and sequential circuits, FSMs, memory interfaces, and basic digital architectures using Verilog HDL, with the option to support VHDL if enabled by the organisers.

Objective: To test participants' understanding of digital logic and RTL design. To develop practical HDL programming skills. To evaluate the ability to design combinational and sequential circuits. To test problem-solving under strict time constraints. To encourage efficient, readable, and synthesis-ready HDL code. To provide practical exposure to digital-system design and simulation.

Problem Statement: Participants will be given 10 digital design problems covering combinational logic, sequential circuits, finite state machines, memory interfaces, and basic processor components. Participants must develop correct, synthesis-ready solutions using only Verilog or VHDL within the given time limit. Solutions will be evaluated using suitable HDL simulators and testbenches against predefined or hidden test cases.

Event Details: Participants will individually solve 10 HDL-based digital design problems within a fixed time limit of 1 hour .

Questions may include: Combinational logic Sequential circuits Counters and registers FSMs Memory interfaces Basic processor components Participants may use only Verilog or VHDL. The challenge will be conducted offline without internet or AI assistance.

Evaluation: Submitted solutions will be tested using suitable HDL simulators/compilers against testbenches. Participants will be evaluated based on functional correctness, optimisation, readability, and testbench implementation where applicable.

Rules and Regulations: Participation is individual only. Participants must carry a valid student ID. Only Verilog or VHDL is allowed. No other HDL or programming language will be permitted. The competition will be conducted in offline mode. Internet access, mobile phones, and smartwatches are not permitted. No AI assistance is permitted during the challenge. Participants must write all code during the event. Pre-written code snippets, templates, or solutions are not allowed. Plagiarism or use of pre-existing code will result in disqualification. Participants must use the HDL and simulation environment specified by the organisers. Misbehaviour may result in disqualification. The coordinators' decision will be final.